1. Field of the Invention
The present invention relates to a package module for an IC device and, more specifically, to a method of forming a package module for at least one IC device.
2. Discussion of the Background
A typical conventional flip-chip package is usually a bumped die attached onto a multi-layer substrate. Please refer first to FIG. 1, which schematically illustrates the cross-sectional diagram of the flip chip package module in accordance with the prior art. The flip chip package module generally consists of a substrate (1), a semiconductor (2), a plurality of bumps (3), an underfill layer (4), and a plurality of solder balls (5).
The substrate (1) is usually comprised of multiple-layers (4 or 6 layers) that are interconnected and the substrate comprises of a first surface (1a), a second surface (1b), a plurality of conductive vias (6), and a plurality of solder pads (7). The semiconductor device (2), having a plurality of die pads, is connected to the substrate (1) by means of wafer bumps, which can be solder bumps or other types of bumps. The die pads are first coated with layers of UBM (Under Bump Metallurgy, not shown in the figure) before applying the bumps (3). After the bumps (3) are formed on the semiconductor device (2), the semiconductor device (2) is attached onto the substrate (1) for electrical contact. The underfill layer (4), is filled into the gaps and cured between the substrate (1) and the semiconductor device (2), providing better mechanical strength. The solder balls (5) are located atop the solder pads (7) on the second surface (1b) of the substrate (1).
However, the prior art has the following disadvantages:
According to conventional packaging technology, layers of UBM (Under Bump Metallurgy) must be formed on the die pads before applying the wafer bumps. After forming the bumps, the semiconductor device is adhered to the first surface of the substrate. Moreover, bumps must be formed for electrical contacts with the substrate thereunder. The process of making UBM layers and bumps is costly.
2. The substrate in the prior art usually contains four or six layers, and at least two layers are required to avoid warpage and bending of the substrate. Therefore, the manufacturing process of the conventional substrate is very costly.
3. The probe card for the chip probe test of the bumped wafer is more expensive than a conventional probe card for bare wafers with bare probe pads on each die.
4. Most substrates are composed of organic material, and their CTE (Coefficient of Thermal Expansion) is around 18 ppm/° C., which is much higher than that of the die (CTE around 4 ppm/° C.). This mismatch of CTE values poses a threat to temperature-cycle reliability, particularly for large-area dies.
5. Due to the low viscosity requirement for the underfill liquid (before curing), the choice of underfill materials is limited. A consequence is that the moisture resistance of the cured underfill material is not as great as certain epoxy compounds or certain organic compounds serving as glues.
Based on the abovementioned drawbacks, it becomes an important issue to conceive a new package module of IC devices and a method of fabricating the same to minimize production costs and to increase manufacturing yields for semiconductor assembly technology.